Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

Blog Article

Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip.In conventional multiprocessors, this mapping is Jeans area-agnostic as the cores in the core graph are uniform and therefore iso-area.This changes for Systems-on-Chip because tasks are mapped to specific blocks and not general-purpose cores.Thus, the area of these specific cores is varying.This requires novel mapping methods.

In this paper, we propose a an area-aware cost function for simulated annealing; Furthermore, we advocate the use of nonlinear models as the area is nonlinear: A semi-definite craggy range sauvignon blanc 2022 program (SDP) can be used as it is sufficiently fast and shows 20% better area than conventional linear models.Our cost function allows for up to 16.4% better area, 2% better communication (bandwidth times hop distance) and 13.8% better total bandwidth in the network in comparison to the standard approach that accounts for both the network communication and uses cores with varying areas as well.